參數(shù)資料
型號(hào): SPAK56F807VF80
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝: MOLD ARRAY PROCESS, BGA-160
文件頁數(shù): 20/48頁
文件大小: 853K
代理商: SPAK56F807VF80
Reset, Stop, Wait, Mode Select, and Interrupt Timing
MOTOROLA
DSP56F807 Preliminary Technical Data
27
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
,5
Figure 13. External Bus Asynchronous Timing
Table 31. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50 pF
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See
Figure
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
ns
RESET De-assertion to First External Address Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
ns
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
tIDM
15T
ns
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
16T
ns
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
13T
ns
IRQA Width Assertion to Recover from Stop State4
tIW
—2T
ns
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data In
Data Out
tAWR
tARDA
tARDD
tRDA
tRD
tRDRD
tRDWR
tWRWR
tWR
tDOS
tWRD
tWRRD
tAD
tDOH
tDRD
tRDD
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