參數資料
型號: SN74BCT8373NT
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: BCT/FBT SERIES, 8-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDIP24
文件頁數: 7/21頁
文件大小: 287K
代理商: SN74BCT8373NT
SN74BCT8373
SCAN TEST DEVICE
WITH OCTAL DTYPE LATCHES
SCBS471 JUNE 1990 REVISED JUNE 1994
215
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
timing description
All test operations of the SN74BCT8373 are synchronous to TCK. Data on the TDI, TMS, and normal-function
inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals
on the falling edge of TCK. The TAP controller is advanced through its states (as illustrated in Figure 1) by
changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is illustrated in Figure 8. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan
and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO
is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 4 explains
the operation of the test circuitry during each TCK cycle.
Table 4. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
TDO becomes active on the falling edge of TCK. The IR captures the 8-bit binary value 10000001 on the rising
edge of TCK as the TAP controller exits the Capture-IR state.
6
Shift-IR
TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as
the TAP controller advances to the next state.
713
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK
cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
14
Exit1-IR
15
Update-IR
The IR is updated with the new instruction (BYPASS) and TDO becomes inactive (goes to the high-impedance
state) on the falling edge of TCK.
16
Select-DR-Scan
17
Capture-DR
TDO becomes active on the falling edge of TCK. The bypass register captures a logic 0 value on the rising
edge of TCK as the TAP controller exits the Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on
the rising edge of TCK as the TAP controller advances to the next state.
19 20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
22
Update-DR
In general, the selected data register is updated with the new data and TDO becomes inactive (goes to the
high-impedance state) on the falling edge of TCK.
23
Select-DR-Scan
24
Select-IR-Scan
25
Test-Logic-Reset
Test operation completed
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