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參數(shù)資料
| 型號： | SMH4804 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | -48V Programmable Hot Swap Sequencing Power Controller |
| 中文描述： | - 48V的可編程序熱插拔電源控制器 |
| 文件頁數(shù)： | 34/41頁 |
| 文件大?。?/td> | 574K |
| 代理商： | SMH4804 |
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Registers
SMH4804
34
2050 3.7 10/30/02
Summit Microelectronics
Register 5 - Address 0101
Register 5 controls the function of the nonvolatile fault latch and provides general control for the FS# input. Bit
3 controls the enabling of the non-volatile latch. Bits 2:0 configure the FS# input.
The FS# pin has two basic functions: it can be programmed to act as an auxiliary enable input controlling the
PG1# output, or it can be programmed to be an event monitor during the power-up sequence.
These bits also control the interrelationship of the PG[4:1]
#
outputs. In a cascade operating mode PG1# must
be true before PG2# can be true, etc. This interrelationship can be disabled so that each PG[4:1]# output is
effectively controlled by its corresponding ENGPx# input, as long as the primary supply, VGATE and DRAIN
SENSE pins are within their operating limits.
When programmed as an enable to PG1# there are two options: 010
BIN
disables the cascade mode (the
PG[4:1]# outputs can act independently) and FS# effectively becomes the enable input for PG1#; 011
BIN
enables the cascade mode and makes FS# the enable input for PG1#. In this mode, PG1# must be active before
PG2# can be activated, followed by PG3#, then PG4#.
The event monitor mode is generally implemented in conjunction with a monitoring device on the secondary side
of the DC/DC converters, such as the SMS44, SMT4004 or SMS64. If FS# is not pulled high before the
programmed condition then the PG[4:1]# and VGATE outputs are shut down. As an example, if the binary value
is 111
BIN
, VGATE and PG1# are shut down if FS# is not pulled high before t
PGD
has elapsed after PG1# is true.
None of the other PG[4:1]# outputs are activated. If a failure occurs due to the lapse of the event monitor timer,
cycling the power resets the device.
Bits
Default
R/W
Description
3
2
1
0
0
0b1
R/W
When bit 3 is cleared, the non-volatile latch is enabled.
1
When bit 3 is set, the non-volatile latch is disabled.
0
0
0
0b100
R/W
When bits 2:0 are 0b000, the FS function: PG4 + t
PGD
cascade
is disabled for simultaneous assertion of the PG[4:1]# pins.
0
0
1
When bits 2:0 are 0b001, the FS function is disabled (=1).
0
1
0
When bits 2:0 are 0b010, the FS function is active (=1) before
PG1 enabled. Cascade disabled for simultaneous assertion of
the PG[4:1]# pins.
0
1
1
When bits 2:0 are 0b011, the FS function must be high (de-
asserted) before PG1 is enabled.
1
0
0
FS function: PG4 + t
PGD
(PG Delay)
1
0
1
FS function: PG3 + t
PGD
(PG Delay)
1
1
0
FS function: PG2 + t
PGD
(PG Delay)
1
1
1
FS function: PG1 + t
PGD
(PG Delay)
Table 6. Register 5 Bitmap
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PDF描述 |
|---|---|
| SMH4812 | Distributed Power Hot-Swap Controller |
| SMH4812G | Distributed Power Hot-Swap Controller |
| SMH4812S | Distributed Power Hot-Swap Controller |
| SMH4814 | Dual Feed Active-ORing Programmable Hot Swap Controller |
| SMH4814NCR00 | Dual Feed Active-ORing Programmable Hot Swap Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMH4804F | 制造商:SUMMIT 功能描述: |
| SMH4811 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DISTRIBUTED POWER HOT SWAP CONTROLLER |
| SMH4811A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DISTRIBUTED POWER HOT SWAP CONTROLLER |
| SMH4811A_09 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Programmable Distributed Power Hot-Swap Controller for High-Availability Systems |
| SMH4811AG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DISTRIBUTED POWER HOT SWAP CONTROLLER |
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