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參數(shù)資料
| 型號(hào)： | SMH4804 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | -48V Programmable Hot Swap Sequencing Power Controller |
| 中文描述： | - 48V的可編程序熱插拔電源控制器 |
| 文件頁數(shù)： | 27/41頁 |
| 文件大小： | 574K |
| 代理商： | SMH4804 |
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SMH4804
Programming Information
Summit Microelectronics
2050 3.7 10/30/02
27
–
PROGRAMMING INFORMATION
I
2
CBus Interface
The I
2
C bus is a two-way, two-line serial communication
between different integrated circuits. The two lines are: a
serial data line (SDA) and a serial clock line (SCL). The
SMH4804 supports a 100 kHz clock rate.
The SDA line must be connected to a positive supply by a
pull-up resistor located on the bus. The SMH4804 contains
a Schmitt input on both the SDA and SCL signals.
Start and Stop Conditions
Both the SDA and SCL pins remain high when the bus is not
busy. Data transfers between devices may be initiated with
a Start condition only when SCL and SDA are high. A high-
to-low transition of the SDA while the SCL pin is high is
defined as a Start condition. A low-to-high transition SDA
while SCL is high is defined as a Stop condition. Figure 20
shows a timing diagram of the start and stop conditions.
Figure 20. Start and Stop Conditions
Master/Slave Protocol
The master/slave protocol defines any device that sends
data onto the bus as a transmitter, and any device that
receives data as a receiver. The device controlling data
transmission is called the Master, and the controlled device
is called the Slave. In all cases the SMH4804 is referred to
as a Slave device since it never initiates any data transfers.
Acknowledge
Data is always transferred in bytes. Acknowledge (ACK) is
used to indicate a successful data transfer. The transmitting
device releases the bus after transmitting eight bits. During
the ninth clock cycle the Receiver pulls the SDA line low to
acknowledge that it received the eight bits of data. This is
shown by the ACK callout in Figure 21.
When the last byte has been transferred to the Master
during a read of the SMH4804, the Master leaves SDA high
for a Not Acknowledge (NACK) cycle. This causes the
SMH4804 part to stop sending data, and the Master issues
a Stop on the clock pulse following the NACK.
Figure 21 shows the Acknowledge timing.
Figure 21. Acknowledge Timing
Read and Write
The first byte from a Master is always made up of a 7-bit
Slave address and the Read/Write (R/W) bit. The R/W bit
tells the Slave whether the Master is reading data from the
bus or writing data to the bus (1 = Read, 0 = Write). The first
four of the seven address bits are called the Device Type
Identifier (DTI). The DTI for the SMH4804 is 1010
BIN
.
The
next three bits are Address values for A2, A1, and A0 (if
multiple devices are used). The SMH4804 issues an
Acknowledge after recognizing a Start condition and its DTI.
Figure 22 shows an example of a typical master address
byte transmission.
Figure 22. Typical Master Address Byte Transmission
During a read by the Master device, the SMH4804 transmits
eight bits of data, then releases the SDA line, and monitors
the line for an Acknowledge signal. If an Acknowledge is
detected, and no Stop condition is generated by the Master,
the SMH4804 continues to transmit data. If an Acknowledge
is not detected (NACK), the SMH4804 terminates any
subsequent data transmission. The read transfer protocol
on SDA is shown in Figure 23.
2050 Fig10 2.0
SCL
SDA In
START
Condition
STOP
Condition
SCL
SDA
Trans
SDA
Rec
1
2
3
8
9
ACK
2050 Fig11
SCL
SDA
1
2
3
8
9
4
5
6
7
1
0
1
R/W
0
x
x
x
ACK
2050 Fig12
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| SMH4811A_09 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Programmable Distributed Power Hot-Swap Controller for High-Availability Systems |
| SMH4811AG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DISTRIBUTED POWER HOT SWAP CONTROLLER |
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