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參數(shù)資料
| 型號： | SME5224AUPA-360 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 360 MHz, RISC PROCESSOR |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 373K |
| 代理商： | SME5224AUPA-360 |
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5
360 MHz CPU, 4.0 MB E-Cache
UltraSPARC-II CPU Module
SME5224AUPA-360
Preliminary Version
July 1999
Sun Microsystems, Inc
SYSTEM INTERFACE
Figure 2 shows the major components of a UPA based uniprocessor system. The system controller [1] for the
UPA bus arbitrates between the UltraSPARC–II, 360 MHz CPU, 4.0 Mbyte E-cache module, and the I/O
bridge chip. It includes a slave-only UPA graphics device for Sun graphics boards.
The module UPA system interface signals run at one-third of the rate of the internal CPU frequency.
UPA Connector Pins
The UPA edge connector provides impedance control. The pin assignments are shown with the physical mod-
ule connector and are represented on page 24 and page 25.
UPA Interconnect
The UltraSPARC–II, 360 MHz CPU, 4.0 Mbyte E-cache module, (SME5224AUPA-360), supports full master
and slave functionality with a 128-bit data bus and a 16-bit error correction code (ECC).
All signals that interface with the system are compatible with LVTTL levels. The clock inputs at the module
connector, CPU_CLK, UPA_CLK0, and UPA_CLK1, are differential low-voltage PECL compatible.
1. Only two megabytes of external cache are recognized and supported when using the
Dual Processor System Controller (DSC, Marketing Part No.STP2202ABGA).
Figure 2. Uniprocessor System Conguration
I/O Bridge
Chip
UltraSPARC-II
Module
SME5224AUPA-360
Memory
SIMMs
Memory Data Bus
Cross Bar
Switch
UPA Address Bus 0
UPA Data Bus
144
72
UPA Data Bus
72
Expansion Bus
UPA
Graphic
Device
System
Controller
UPA Address Bus 1
UPA Data Bus
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