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參數(shù)資料
| 型號： | SME5224AUPA-360 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 360 MHz, RISC PROCESSOR |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 373K |
| 代理商： | SME5224AUPA-360 |
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3
360 MHz CPU, 4.0 MB E-Cache
UltraSPARC-II CPU Module
SME5224AUPA-360
Preliminary Version
July 1999
Sun Microsystems, Inc
DATA BUFFER DESCRIPTION
UltraSPARC-II Data Buffer (UDB-II)
The UltraSPARC-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for
a UPA interconnect system bus width of 128 Data + 16 ECC.
There is a bidirectional ow of information between the external cache of the CPU and the 144-bit UPA inter-
connect. The information ow is linked through the UDB-II, it includes: cache ll requests, writeback data for
dirty displaced cache lines, copyback data for cache entries requested by the system, non-cacheable loads and
stores, and interrupt vectors going to and from the CPU.
Each UDB-II has a 64-bit interface plus eight parity bits on the CPU side, and a 64-bit interface plus eight error
correction code (ECC) bits on the system side.
The CPU side of the UDB-II is clocked with the same clock delivered to UltraSPARC-II (1/2 of the CPU pipe-
line frequency).
EXTERNAL CACHE DESCRIPTION
The external cache (E-cache) is connected to the E-cache data bus. Nine SRAM chips are used to implement
the four megabyte E-cache. One SRAM is used as the tag SRAM and eight are used as data SRAMs. The tag
SRAM is 128K x 36, while the data SRAMs are 256K x 18. All nine SRAMs operate in a synchronous regis-
ter-latch mode.
The SRAM interface to the CPU runs at one-half of the frequency of the CPU pipeline. The SRAM signals
operate at 1.9V HSTL. The SRAM clock is a differential low-voltage HSTL input. [1]
1. PECL (Positive Emitter Coupled Logic) clocks are converted on the module to the HSTL clocks, for the E-cache
interface.
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