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參數(shù)資料
| 型號： | SMARTPSE24-KIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL REF 24PORT SPI/UART |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電源管理，以太網(wǎng)供電（POE），PSE |
| 已用 IC / 零件： | Si3452，Si3482，Si3500 |
| 已供物品： | 板，線纜，CD |
| 相關(guān)產(chǎn)品： | SI3482-A01-GM-ND - IC CTLR POE 24-48PORT PSE 24-QFN 336-1830-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1835-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1829-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1831-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1834-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1844-5-ND - IC POE SWITCH PWR OVER LAN 20QFN 336-1833-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1832-5-ND - IC POE CONTROLLER MIDSPAN 40QFN |
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Si3452
Rev. 1.3
15
4.8. SMBus/I2C Interface Description
The I2C interface is a two-wire, bidirectional serial bus. The I2C is compliant with the System Management Bus
Specification (SMBus), version 1.1 and compatible with the I2C serial bus. Reads and writes to the interface by the
system controller are byte-oriented with the I2C interface autonomously controlling the serial transfer of the data. A
method of extending the clock-low duration is available to accommodate devices with different speed capabilities
on the same bus. The I2C provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation.
A typical I2C transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address;
Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a master
or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see Figure 6). If the receiving device
does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high
SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic
1 to indicate a “READ” operation and cleared to logic 0 to indicate a “WRITE” operation. All transactions are
initiated by a master, with one or more addressed slave devices as the target. The master generates the START
condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the
master to the slave, the master transmits the data one byte at a time, waiting for an ACK from the slave at the end
of each byte.
For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At
the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus.
Silicon Laboratories recommends the use of bidirectional digital isolators, such as the Si840x, to isolate the I2C
communications interface between the Si3452 high-voltage port controllers and the system host controller.
Figure 6. Typical I2C Bus Transactions
The Si3452 does not support the alert response address (ARA) protocol. Polling is used to determine which
controller is interrupting in an interrupt-driven system.
0
1
0
A3A2 A1A0 R/W#
ACK by IC
A7 A6 A5 A4 A3 A2 A1 A0
ACK by IC
D7 D6 D5 D4 D3 D2 D1 D0
ACK by IC
STOP by Master
START
Fixed IC
Address
Pin Set IC
Address
Slave Address
Register Address
Write Data
01
0
A3 A2 A1 A0 R/W#
ACK by IC
A7 A6 A5 A4 A3 A2 A1 A0
ACK by IC
START
Fixed IC
Address
Pin Set IC
Address
Slave Address
Register Address
Setup Register Address
START
0
1
0
A3A2 A1A0 R/W#
ACK by IC
D7 D6 D5 D4 D3 D2 D1 D0
Not ACK by Master
STOP by Master
Fixed IC
Address
Pin Set IC
Address
Slave Address
Register Data
Transfer Data to Setup Address
Write Sequence
Read Sequence
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