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參數(shù)資料
| 型號(hào)： | SMARTPSE24-KIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/36頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL REF 24PORT SPI/UART |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電源管理，以太網(wǎng)供電（POE），PSE |
| 已用 IC / 零件： | Si3452，Si3482，Si3500 |
| 已供物品： | 板，線纜，CD |
| 相關(guān)產(chǎn)品： | SI3482-A01-GM-ND - IC CTLR POE 24-48PORT PSE 24-QFN 336-1830-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1835-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1829-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1831-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1834-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1844-5-ND - IC POE SWITCH PWR OVER LAN 20QFN 336-1833-5-ND - IC POE CONTROLLER MIDSPAN 40QFN 336-1832-5-ND - IC POE CONTROLLER MIDSPAN 40QFN |
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Si3452
Rev. 1.3
13
4.2. Classification
Following a successful PD detection, the classification phase will be automatically initiated in all operational
modes. During this phase, a single measurement will be made at 18 V to determine how much power the PD
device will draw under maximum loads per the IEEE 802.3af and 802.3at standards. The current limit during this
test mode is 60 mA nominal.
The Si3452 supports 1-Event and 2-Event classification. When operating in PoE (<15.4 W) mode, 1-Event
classification is used. Operation in PoE+ (>15.4 W) mode results in 2-Event classification probes. The 1-Event
classification is compliant to IEEE standard 802.3-2005. 2-Event classification is compliant to draft IEEE P802.3at.
4.3. Port Turn-On and Power FETs
The FET is turned on with a gate drive that results in a very low-noise turn-on waveform with a slew rate of less
than 1 V/sec (See Figure 5).
The power FET switch on each port has been sized to have a typical ON resistance of approximately 0.3
. The
shunt resistor for current measurement has also been set to 0.1
. Including interconnection and process variation,
the total resistance to VEE for a port that is on is 0.6
(max). This limits the maximum power dissipation per
channel to < 250 mW when the operating current is 600 mA, the maximum current allowed by the IEEE 802.3at
PoE+ standard.
The FET has a programmable operating current limit. Each channel can be set to support output currents of
400 mA or 800 mA minimum.
In addition to the normal current limit, there is a short circuit current shutdown approximately 25% greater than the
nominal current limit. If there is a transient current surge where the current ramps up faster than the programmed
current limit can respond, the gate drive voltage is clamped immediately to VEE. The clamp is enabled for at least
10 s, which allows the normal current circuitry to respond.
Another important protection feature is foldback current limiting. When VOUT is near VEE, the current limit is at
maximum. As the VDS of the driver switch increases (and VOUT is closer to ground), the current limit goes to its
lowest level. The amount of the foldback current is scaled proportionally with the programmed current limit.
Figure 5. Turn-On Waveform—Vport Relative to GND
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