I
參數(shù)資料
型號(hào): SMARTPSE24-KIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 33/36頁
文件大?。?/td> 0K
描述: KIT EVAL REF 24PORT SPI/UART
標(biāo)準(zhǔn)包裝: 1
主要目的: 電源管理,以太網(wǎng)供電(POE),PSE
已用 IC / 零件: Si3452,Si3482,Si3500
已供物品: 板,線纜,CD
相關(guān)產(chǎn)品: SI3482-A01-GM-ND - IC CTLR POE 24-48PORT PSE 24-QFN
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Si3452
6
Rev. 1.3
Table 4. Detection Specifications
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Detection Current Limit
ILIM_DET
Measured with DETn
shorted to GND
—3
5
mA
Detection Voltage,
when RDET =25k
VDET1
VDET2
VDET3
–10.0
–4.0
–8.0
–4.0
–2.8
–2.8
V
Detection Slew Rate
0.1
V/μs
Detection Probe Duration
TPROBE
10
30
ms
Detection Probe Cycle Time
TDET
——
500
ms
Minimum Valid Signature Resistance
RDET_MIN
15
19
k
Maximum Valid Signature Resistance
RDET_MAX
26.5
33
k
Resistance at which Open Circuit is
Declared
ROPEN
100
400
k
Resistance at which Short Circuit is
Declared
RSHORT
150
400
W
Valid Detect Capacitance
CDET_VALID
——
150
nF
Invalid Detect Capacitance
CDET_INVALD
10
μF
Table 5. Classification Specifications
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Class Event Voltage
VCLASS
0mA < IPort < 45 mA
–20.5
–15.5
V
Mark Event Voltage
VMARK
0mA < IPort < 5 mA
–7
–10
V
Classification Current
Limit
ILIM_CLASS
Measured with DETn shorted to
GND
51
100
mA
Classification Current
Regions
Class 0
Class 1
Class 2
Class 3
Class 4
Overcurrent
0
8
16
25
35
51
5
13
21
31
45
mA
Classification Delay
TCLASS_DLY
Time from end of valid detect cycle
to classification begin
—5—
ms
Classification Event
Time
TCLE
Width of valid VCLASS probe for 1-
Event or 2-Event classification
10
30
ms
Mark Event Time
TME
Width of mark between classification
events
—8—
ms
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