參數(shù)資料
型號: SMARTPSE24-KIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/36頁
文件大?。?/td> 0K
描述: KIT EVAL REF 24PORT SPI/UART
標準包裝: 1
主要目的: 電源管理,以太網(wǎng)供電(POE),PSE
已用 IC / 零件: Si3452,Si3482,Si3500
已供物品: 板,線纜,CD
相關(guān)產(chǎn)品: SI3482-A01-GM-ND - IC CTLR POE 24-48PORT PSE 24-QFN
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336-1829-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1831-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
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336-1844-5-ND - IC POE SWITCH PWR OVER LAN 20QFN
336-1833-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1832-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
Si3452
Rev. 1.3
21
0x0F
Por
t2
I
CUT
R
W
B7
B6
B5
B4
B
3
B2
B1
B0
0x
7
5
0x10
Por
t3
I
CUT
R
W
B7
B6
B5
B4
B
3
B2
B1
B0
0x
7
5
0x1
1
Por
t4
I
CUT
R
W
B7
B6
B5
B4
B
3
B2
B1
B0
0x
7
5
Glob
al
Devi
ce
0x12
C
ommand
Reg-
is
ter
WO
C
M
D
Code
B5
C
M
D
Code
B4
CMD
Code
B
3
CM
D
Code
B2
CM
D
Pa
ra
m
B1
CMD
Par
am
B0
0x0
0
0x13
V
EE
MSB
R
O
0x0
0
0x14
V
EE
LSB
R
O
0x0
0
0x15
C
urre
nt
P1
MSB
RO
0x0
0
0x16
Cur
rent
P1
LSB
R
O
0x0
0
0x17
C
urre
nt
P2
MSB
RO
0x0
0
0x18
Cur
rent
P2
LSB
R
O
0x0
0
0x19
C
urre
nt
P3
MSB
RO
0x0
0
0x1A
Cur
rent
P3
LSB
R
O
0x0
0
0x1B
C
urre
nt
P4
MSB
RO
0x0
0
0x1C
Cur
rent
P4
LSB
R
O
0x0
0
0x1D
Device
S
tatus
RO
Over
Te
mp
V
EE
UVLO
Alter
native
B
Ti
m
in
g
0x0
0
T
a
ble
19.
Si3452
Reg
ister
Ma
p
(Continued)
Ad
dress
Reg
ister
Na
me
T
y
pe
B7
B6
B5
B4
B3
B2
B1
B0
Regist
er
Con
ten
tat
Power
Up
No
tes:
1.
R
egister
conten
tat
Power
Up
is
shown
fo
rthe
Si3452
Shut
do
wn
Mode
p
art.
Refe
rto
"
12.
Or
dering
Guide"
on
p
age
33
to
or
der
Aut
o
Mode
p
ar
ts
with
dif
fere
nt
default
se
ttings.
T
his
register
can
be
cha
nged
via
th
ehost
.Refer
to
Ta
b
le
17
o
np
age
18
for
re
gister
var
iations.
2.
B0
Alterna
tive
B
timing
is
set
to
0x01
if
using
Alter
native
B
de
tect
timing.
Refer
to
"5.6
.Device
S
tatus
Register
(0x1D)"
on
p
ag
e19
and
"
12.
Ordering
Guide"
on
p
age
33.
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