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參數(shù)資料
| 型號(hào)： | SM320C6201BGLPW20 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
| 封裝： | CERAMIC, MO-156, BGA-429 |
| 文件頁數(shù)： | 48/66頁 |
| 文件大?。?/td> | 971K |
| 代理商： | SM320C6201BGLPW20 |
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
52
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP§ (see Figure 32)
NO
PARAMETER
C6201B
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input
3
10
ns
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
*C – 1.6
*C + 1
ns
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
*–2.5
3
ns
9
t
Dela time CLKX high to internal FSX alid
CLKX int
*–2
3
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext
*3
*9
ns
12
t
Disable time, DX high impedance following last data bit from
CLKX int
*–1
*4
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high im edance following last data bit from
CLKX high
CLKX ext
*3
*9
ns
13
t
Dela time CLKX high to DX alid
CLKX int
*–1
*4
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX ext
*3
*9
ns
14
t
Delay time, FSX high to DX valid
FSX int
*–1
*3
ns
14
td(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
*3
*9
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
C = H or L
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
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