參數(shù)資料
型號： SM320C6201BGLPW20
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 200 MHz, OTHER DSP, CBGA429
封裝： CERAMIC, MO-156, BGA-429
文件頁數(shù)： 35/66頁
文件大?。?/td> 971K
代理商： SM320C6201BGLPW20
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 19)
NO
C6201B
UNIT
NO.
MIN
MAX
UNIT
7
tsu(EDV-SDCLKH)
Setup time, read EDx valid before SDCLK high
0.5
ns
8
th(SDCLKH-EDV)
Hold time, read EDx valid after SDCLK high
3
ns
switching characteristics for synchronous DRAM cycles (see Figure 19–Figure 24)
NO
PARAMETER
C6201B
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV-SDCLKH)
Output setup time, CEx valid before SDCLK high
1.5P – 3.5
ns
2
toh(SDCLKH-CEV)
Output hold time, CEx valid after SDCLK high
0.5P – 1
ns
3
tosu(BEV-SDCLKH)
Output setup time, BEx valid before SDCLK high
1.5P – 3.5
ns
4
toh(SDCLKH-BEIV)
Output hold time, BEx invalid after SDCLK high
*0.5P – 1
ns
5
tosu(EAV-SDCLKH)
Output setup time, EAx valid before SDCLK high
1.5P – 3.5
ns
6
toh(SDCLKH-EAIV)
Output hold time, EAx invalid after SDCLK high
*0.5P – 1
ns
9
tosu(SDCAS-SDCLKH)
Output setup time, SDCAS valid before SDCLK high
1.5P – 3.5
ns
10
toh(SDCLKH-SDCAS)
Output hold time, SDCAS valid after SDCLK high
0.5P – 1
ns
11
tosu(EDV-SDCLKH)
Output setup time, EDx valid before SDCLK high
1.5P – 3.5
ns
12
toh(SDCLKH-EDIV)
Output hold time, EDx invalid after SDCLK high
*0.5P – 1
ns
13
tosu(SDWE-SDCLKH)
Output setup time, SDWE valid before SDCLK high
1.5P – 3.5
ns
14
toh(SDCLKH-SDWE)
Output hold time, SDWE valid after SDCLK high
0.5P – 1
ns
15
tosu(SDA10V-SDCLKH)
Output setup time, SDA10 valid before SDCLK high
1.5P – 3.5
ns
16
toh(SDCLKH-SDA10IV)
Output hold time, SDA10 invalid after SDCLK high
*0.5P – 1
ns
17
tosu(SDRAS-SDCLKH)
Output setup time, SDRAS valid before SDCLK high
1.5P – 3.5
ns
18
toh(SDCLKH-SDRAS)
Output hold time, SDRAS valid after SDCLK high
0.5P – 1
ns
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
*Not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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