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參數(shù)資料
| 型號： | SM320C6201BGLPW20 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
| 封裝： | CERAMIC, MO-156, BGA-429 |
| 文件頁數(shù)： | 39/66頁 |
| 文件大?。?/td> | 971K |
| 代理商： | SM320C6201BGLPW20 |
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles (see Figure 25)
NO
C6201B
UNIT
NO.
MIN
MAX
UNIT
1
tsu(HOLDH-CKO1H)
Setup time, HOLD high before CLKOUT1 high
*1
ns
2
th(CKO1H-HOLDL)
Hold time, HOLD low after CLKOUT1 high
*4
ns
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
*Not production tested.
switching characteristics for the HOLD/HOLDA cycles (see Figure 25)
NO
PARAMETER
C6201B
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
3
tR(HOLDL-BHZ)
Response time, HOLD low to EMIF Bus high impedance
*4P
§
ns
4
tR(BHZ-HOLDAL)
Response time, EMIF Bus high impedance to HOLDA low
*P
*2P
ns
5
tR(HOLDH-HOLDAH) Response time, HOLD high to HOLDA high
*4P
*7P
ns
6
td(CKO1H-HOLDAL)
Delay time, CLKOUT1 high to HOLDA valid
*1
8
ns
7
td(CKO1H-BHZ)
Delay time, CLKOUT1 high to EMIF Bus high impedance
*3
*11
ns
8
td(CKO1H-BLZ)
Delay time, CLKOUT1 high to EMIF Bus low impedance
*3
*11
ns
9
tR(HOLDH-BLZ)
Response time, HOLD high to EMIF Bus low impedance
*3P
*6P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
DSP Owns Bus
External Requester
DSP Owns Bus
’C62x
Ext Req
’C62x
8
7
3
4
6
1
2
CLKOUT1
HOLD
HOLDA
EMIF Bus
1
5
9
2
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 25. HOLD/HOLDA Timing
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