參數(shù)資料
型號(hào): SM320C40TABS60/10
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-BIT, 60 MHz, OTHER DSP, UUC325
封裝: TAB-325
文件頁數(shù): 42/64頁
文件大小: 1155K
代理商: SM320C40TABS60/10
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
47
P
ARAMETER
MEASUREMENT
INFORMA
TION
(L)P
AGE0
(L)P
AGE1
(see
Note
C)
Control
Signals
(see
Note
C)
(L)Dx
(see
Note
A)
RESET
(see
Notes
E
and
F)
1
2.1
4.1
6
7
8
3
2.2
4.2
ControlSignals
7
X2/CLKIN
H1
H3
(L)Ax
(see
Note
B)
IACK
Asynchronous
Reset
Signals
(see
Note
D)
Asynchronous
Reset
Signals
(see
Note
E)
T
en
H1
Clock
Cycles
5
9
10
Hi-Z
NOTES:
A.
In
this
figure,
(L)Dx
includes
D31D0,
LD31D0,
and
CxD7CxD0.
B.
(L)Ax
includes
A30A0
and
LA30
LA0.
C.
Control
signals
LSTRB0
,LSTRB1
,STRB0
,STRB1
,(L)ST
A
T3(L)ST
A
T0,
(L)LOCK
,(L)R/W
0,
and
(L)R/W
1
go
high
while
(L)P
AGE0
and
(L)P
AGE1
go
low
.
D.
Asynchronous
reset
signals
that
go
into
high
impedance
after
RESET
goes
low
include
TCLK0,
TCLK1,
IIOF3
IIOF0
,and
the
communication-port
control
signals
CREQx
,CACKy
,CSTRBy
,and
CRDYx
(where
x
=
0,
1,
or
2,
and
y
=
3,
4,
or
5).
(A
treset,
ports
0,
1,
and
2
become
outputs,
and
ports
3,
4,
and
5
become
inputs.)
E.
Asynchronous
reset
signals
that
go
to
a
high-logic
level
after
RESET
goes
low
include
CREQy
,CACKx
,CSTRBx
,and
CRDYy
(where
x
=
0,
1,
or
2,
and
y
=
3,
4,
or
5).
F.
RESET
is
an
asynchronous
input
and
can
be
asserted
at
any
point
during
a
clock
cycle.
If
the
specified
timings
are
met,
the
exact
se
quence
shown
will
occur;
otherwise,
an
additional
delay
of
one
clock
cycle
can
occur
.
Figure
20.
RESET
T
iming
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