參數(shù)資料
型號(hào)： SM320C40TABS60/10
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 60 MHz, OTHER DSP, UUC325
封裝： TAB-325
文件頁(yè)數(shù)： 41/64頁(yè)
文件大小： 1155K
代理商： SM320C40TABS60/10
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
timing parameters of IIOFx changing from input to output mode (see Figure 19)
NO.
320C40-40
320C40-50
320C40-60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
1
td(H1L-IFIO)
Delay time, H1 low to IIOFx switching from input to output
16
14
ns
Execution of
Load of IIOF
1
H3
H1
TYPE Bit
IIOFx pins
Figure 19. Change of IIOFx From Input to Output Mode
timing parameters for RESET (see Figure 20)
NO.
320C40-40
320C40-50
320C40-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1
tsu(RESET-CIL)
Setup time, RESET before CLKIN low
11
tc(CI)
11
tc(Cl)*
11
tc(Cl)*
ns
2.1
td(CIH-H1H)
Delay time, CLKIN high to H1 high
2
12
2
10
2
10
ns
2.2
td(CIH-H1L)
Delay time, CLKIN high to H1 low
2
12
2
10
2
10
ns
3
tsu(RESETH-H1L)
Setup time, RESET high before H1 low and
after ten H1 clock cycles
13
ns
4.1
td(CIH-H3L)
Delay time, CLKIN high to H3 low
2
12
2
10
2
10
ns
4.2
td(CIH-H3H)
Delay time, CLKIN high to H3 high
2
12
2
10
2
11
ns
5
tdis(H1H-DZ)
Disable time, H1 high to (L)Dx in
high-impedance state
13*
ns
6
tdis(H3H-AZ)
Disable time, H3 high to (L)Ax in
high-impedance state
9*
ns
7
td(H3H-CONTROLH)
Delay time, H3 high to control signals high
[low for (L)PAGEx]
9*
ns
8
td(H1H-IACKH)
Delay time, H1 high to IACK high
9*
ns
9
tdis(RESETL-ASYNCHZ)
Disable time, RESET low to asynchronous
reset signals in the high-impedance state
21*
ns
10
td(RESETH-COMMH)
Delay time, RESET high to asynchronous reset
signals high
15*
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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