參數(shù)資料
型號: SL811HST
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: Embedded USB Host/Slave Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 10/29頁
文件大?。?/td> 499K
代理商: SL811HST
SL811HS
Document #: 38-08008 Rev. *A
Page 10 of 29
Bit 3 is reserved for future usage.
The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted. When this bit set
1,
the next
enabled packet will be sent after next SOF. If set =
0
the next packet is sent immediately if the SIE is free.
The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only used to send packets to a low-speed
device through a hub. To communicate to a full speed device, this bit is set to zero. For example, when SL811HS communicates
to a low-speed device via the HUB:
SL811HS SIE should set to operate at 48 MHz, i.e., bit 5 of register 05H should be set =
0.
Bit 6 of register 0FH should be set =
0,
set correct polarity of DATA+ and DATA
state for Full Speed.
Bit 7, Preamble Bit, should be set =
1
in Host Control register.
When SL811HS communicates directly to low-speed device:
SL811HS. Bit 5 of register 05H should be set =
1.
Bit 6 of register 0FH should be set =
1,
DATA+ and DATA
polarity for low speed.
The state of bit 7 is ignored in this mode.
5.2.3
SL811HS memory set-up as shown:
03h-04h Register will contain PID and Device endpoint and Device Address.
10h-FFh USB Data as required.
Example of SL811HS USB Packet Transfer
5.2.1
SL811HS Host Control Registers
Register Name SL11H and SL811H
SL11H (hex)
Address
SL811HS (hex)
Address
USB-A Host Control Register
00H
00H
USB-A Host Base Address
01H
01H
USB-A Host Base Length
02H
02H
USB-A Host PID, Device Endpoint (Write)/USB Status (Read)
03H
03H
USB-A Host Device Address (Write)/Transfer Count (Read)
04H
04H
USB-B Host Control Register
Reserved
08H
USB-B Host Base Address
Reserved
09H
USB-B Host Base Length
Reserved
0AH
USB-B Host PID, Device Endpoint (Write)/USB Status (Read)
Reserved
0BH
USB-B Host Device Address (Write)/Transfer Count (Read)
Reserved
0CH
5.2.2
USB-A/USB-B Host Control Registers [00H, 08H]
Bit Position
Bit Name
Function
0
Arm
Allows enabled transfers when set =
1.
Cleared to
0
when transfer is complete.
1
Enable
When set =
1
allows transfers to this endpoint. When set
0
USB transactions are ignored.
If Enable =
1
and Arm = '0' the endpoint will return NAKs to USB transmissions.
2
Direction
When set =
1
transmit to Host. When
0
receive from Host.
3
Reserved
4
ISO
When set to
1
allows Isochronous mode for this endpoint.
5
SOF
1
= Synchronize with the SOF transfer
6
Data Toggle Bit
0
if DATA0,
1
if DATA1.
7
Preamble
If set =
1
a preamble token is transmitted prior to transfer of low-speed packet. If set =
0,
preamble generation is disabled.
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