參數(shù)資料
型號: SED122ADXA
元件分類: 顯示控制器
英文描述: 16 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC165
封裝: DIE-165
文件頁數(shù): 28/50頁
文件大小: 398K
代理商: SED122ADXA
4–34
EPSON
SED1220
TIMING CHARACTERISTICS
(1)
MPU Bus Write Timing (80 series)
A0
WR
D0 to D7
tAH8
tcyc8
tAC8
tAW8
tCCL
tCCH
tDS8
tDH8
CS
Item
Signal
Symbol
Measuring
Min.
Max.
Unit
condition
Address hold time
A0, CS
tAH8
Every timing is specified
30
ns
Address setup time
tAW8
on the basis of 20% and
60
ns
CS setup time
tAC8
80% of VSS.0
ns
System cycle time
WR
tCYC8
650
ns
Write “L” pulse width (WR)
tCCL
150
ns
Write “H” pulse width (WR)
tCCH
450
ns
Data setup time
D0 ~ D7
tDS8
100
ns
Data hold time
tDH8
50
ns
[Ta = –30 to 85
°C, VSS = –3.6 V to –2.4 V]
Item
Signal
Symbol
Measuring
Min.
Max.
Unit
condition
Address hold time
A0, CS
tAH8
Every timing is specified
10
ns
Address setup time
tAW8
on the basis of 20% and
60
ns
CS setup time
tAC8
80% of VSS.0
ns
System cycle time
WR
tCYC8
500
ns
Write “L” pulse width (WR)
tCCL
100
ns
Write “H” pulse width (WR)
tCCH
350
ns
Data setup time
D0 ~ D7
tDS8
100
ns
Data hold time
tDH8
20
ns
[Ta = –30 to 85
°C, VSS = –3.3 V to –2.7 V]
*1: For the rise and fall of an input signal (tr and tf), set a value not exceeding 25ns (excluding RES input).
*2:
tCCL is specified based on an overlap period of CS and WR “L” levels.
VSS
× 0.8 [V]
VSS
× 0.2 [V]
tr
tf
相關(guān)PDF資料
PDF描述
SED1278FOD 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
SED1278F 16 X 40 DOTS DOT MAT LCD DSPL CTLR, PQFP80
SED1330FBA DOT MAT LCD DSPL CTLR, PQFP60
SED1330FBB 640 X 256 DOTS DOT MAT LCD DSPL CTLR, PQFP60
SED1335FOA DOT MAT LCD DSPL CTLR, PQFP60
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SED1278 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER
SED1278D 制造商:EPSON 制造商全稱:EPSON 功能描述:Dot Matrix LCD Controller Driver
SED1278D0A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER
SED1278D0B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER
SED1278D0C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER