參數(shù)資料
型號(hào)： SDC2800DUT3D
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 2000 MHz, MICROPROCESSOR, CPGA453
封裝： OPGA-453
文件頁數(shù)： 85/102頁
文件大?。?/td> 3049K
代理商： SDC2800DUT3D
Chapter 10
Pin Descriptions
71
31994A—1August 2004
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
signals High above 2.5 V. Do not expose these pins to a
differential voltage greater than 1.60 V, relative to the
processor core voltage.
Refer to “VCC_2.5V Generation Circuit” found in the section,
“Motherboard Required Circuits,” of the AMD Athlon
Processor Motherboard Design Guide, order# 24363 for the
required supporting circuitry.
DC characteristics for FID[3:0].
FSB_Sense[1:0] Pins
FSB_Sense[1:0] pins are either open circuit (logic level of 1) or
are pulled to ground (logic level of 0) on the processor package
with a 1 k
resistor. In conjunction with a circuit on the
motherboard, these pins may be used to automatically detect
the front-side bus (FSB) setting of this processor. Proper
detection of the FSB setting requires the implementation of a
pull-up resistor on the motherboard. Refer to the AMD Athlon
Processor-Based Motherboard Design Guide, order# 24363 and the
technical note FSB_Sense Auto Detection Circuitry for Desktop
Processors, order# TN26673 for more information.
Table 22 is the truth table to determine the FSB of desktop
processors.
The FSB_Sense[1:0] pins are 3.3-V tolerant.
FLUSH# Pin
FLUSH# must be tied to VCC_CORE with a pullup resistor. If a
debug connector is implemented, FLUSH# is routed to the
debug connector.
IGNNE# Pin
IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# Pin
INIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0_FFFF_FFF0h.
Table 22. Front-Side Bus Sense Truth Table
FSB_Sense[1]
FSB_Sense[0]
Bus Frequency
1
0
RESERVED
1
133 MHz
0
1
166 MHz
0
200 MHz
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