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參數(shù)資料
| 型號(hào)： | SDC2800DUT3D |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | OPGA-453 |
| 文件頁(yè)數(shù)： | 22/102頁(yè) |
| 文件大?。?/td> | 3049K |
| 代理商： | SDC2800DUT3D |
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14
Power Management
Chapter 4
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Figure 4 shows STPCLK# assertion resulting in the processor in
the St op Gra nt st ate and the A M D A thlon system bu s
disconnected.
Figure 4. AMD Athlon System Bus Disconnect Sequence in the Stop Grant State
An example of the AMD Athlon system bus disconnect
sequence is as follows:
1. The peripheral controller (Southbridge) asserts STPCLK#
to place the processor in the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, it enters
the Stop Grant state and then issues a Stop Grant special
cycle.
3. When the special cycle is received by the Northbridge, it
deasserts CONNECT, assuming no probes are pending,
initiating a bus disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the
processor enters a low-power state. The Northbridge passes
the Stop Grant special cycle along to the Southbridge.
Stop Grant
STPCLK#
CONNECT
PROCRDY
CLKFWDRST
PCI Bus
AMD Athlon
System Bus
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