參數(shù)資料
型號(hào)： SDC2800DUT3D
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 2000 MHz, MICROPROCESSOR, CPGA453
封裝： OPGA-453
文件頁數(shù)： 32/102頁
文件大?。?/td> 3049K
代理商： SDC2800DUT3D
Chapter 6
333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications
23
31994A—1August 2004
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
6.3
333 FSB AMD Athlon System Bus AC Characteristics
The AC characteristics of the AMD Athlon system bus of this
processor are shown in Table 3. The parameters are grouped
based on the source or destination of the signals involved.
Table 3.
333 FSB AMD Athlon System Bus AC Characteristics
Group
Symbol
Parameter
Min
Max
Units
Notes
All Signals
TRISE
Output Rise Slew Rate
1
3
V/ns
1
TFALL
Output Fall Slew Rate
1
3
V/ns
1
Forward
Clocks
TSKEW-DIFFEDGE
Output skew with respect to a
different clock edge
–
770
ps
2
TSU
Input Data Setup Time
300
ps
3
THD
Input Data Hold Time
300
ps
3
CIN
Capacitance on input clocks
4
25
pF
COUT
Capacitance on output clocks
4
12
pF
Sync
TVAL
RSTCLK to Output Valid
800
2000
ps
4, 5
TSU
Setup to RSTCLK
500
ps
4, 6
THD
Hold from RSTCLK
500
ps
4, 6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include
PROCRDY, CONNECT, and CLKFWDRST.
5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
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