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參數(shù)資料
| 型號(hào)： | SDA9589X |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs |
| 中文描述： | 畫中畫四先進(jìn)SOPHISTICUS高端畫中畫，圖像芯片 |
| 文件頁(yè)數(shù)： | 24/102頁(yè) |
| 文件大?。?/td> | 2306K |
| 代理商： | SDA9589X |
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SDA 9489X
SDA 9589X
System Description
Micronas
4-24
Preliminary Data Sheet
Figure 4-8
Field detection and phase adjustment of vertical pulse (VSP)
Depending on the phase between inset and parent signals a correction of the display
raster for the read out data is performed. As the external VSP and HSP signals may
come from different devices with different delay paths, the phase between V-sync and
H-sync is adjustable (
VSPDEL
). An incorrect setting of
VSPDEL
may result in wrong or
unreliable field detection of parent channel.
Normally a noise reduction of the incoming parent vertical pulse is performed. With this
function missing vertical pulses are compensated. The circuit works for 50/60 Hz
applications as well as progressive and 100/120Hz application. (S)VGA signals are
supposed to be very stable and therefore not supported by the noise suppression. By
means of
VSPNSRQ,
vertical noise suppression is switched off.
A great variety of combinations of inset and parent frequencies are possible. The
following table shows some constellations.
VSPDEL
VSPDEL
max
=151 (75)
←
s
values in brackets () apply for 100Hz systems
field 0 window
field 1 window
tH = 64 (32)
←
s
tH/2 = 32 (16)
←
s
HSP
VSP
VSPD
(internal)
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