參數(shù)資料
型號(hào): SDA9588X
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類(lèi): 畫(huà)面疊加
英文描述: Cost-effective Picture-In-Picture ICs
中文描述: PICTURE-IN-PICTURE IC, PDSO28
封裝: SOIC-28
文件頁(yè)數(shù): 31/87頁(yè)
文件大?。?/td> 2045K
代理商: SDA9588X
SDA 9488X
SDA 9588X
System Description
Micronas
4-31
Preliminary Data Sheet
Figure 4-15
Visualization of RGB/YUV insertion
The external RGB or YUV signals are each clamped to the reference levels of the DACs
to force uniform black levels in each channel. The clamping needs careful adjustment
especially for VGA applications. The position and the length of the blanking pulse as well
as the clamping pulse are adjustable (
CLPPOS, CLPLEN)
. If
READD
is set to ’1’ (100Hz
mode), all pulses are shortened by one half.
HZOOM
influences the adjustment range of
the clamping and blanking pulse because of the modified clock frequency, but the pulse
length is kept nearly constant.
Figure 4-16
PIP horizontal blanking timing
OSD
RGB/VYU
R/V
G/Y
B/U
FSW
SEL
OSD
OSD
OSD
RGBINS='10'
PIPON='1'
RGBINS='00'
PIPON='1'
OSD
OSD
RGBIN='1X'
PIPON='0'
OSD
OSD
RGBINS='11'
PIPON='1'
X
X
H
V
S
S
V
V
I
I
I
I
I
F
S
O
O
O
V
V
V
V
V
PiP IV
C
V
C
V
C
BLANKP
HSP
CLAMPP
a
Parent
Video
allowed
HSP range
256 T
b
d
c
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