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參數(shù)資料
| 型號： | SDA9254-2 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
| 中文描述： | VIDEO DRAM, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大小： | 183K |
| 代理商： | SDA9254-2 |
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SDA 9254-2
Semiconductor Group
2
1998-01-16
Functional Description
General
The SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive recursive filter to
achieve a reduction of noise for video signals. To get a closed loop one of the two output ports of
the triple port memory is connected internally to the noise reduction filter. External access to this
port is not possible. The characteristic of the noise reduction filter is adjustable via three pins
(CLASS2, CLASS1, CLASS0).
Block Diagram
The memory capacity of the SDA 9254-2 enables a field based filtering of 4:1:1 video signals (pin
NR422 = ‘0’). 4:2:2 applications are supported by a special noise reduction mode (pin NR422 = ‘1’).
In this mode filtering is applied only to the luminance signal, the chrominance signals are delayed
by an internal delay line but remain unfiltered. For the storage of 4 bit planes of the chrominance
signal a SDA 9251-2X is requested additionally.
Noise
Reduction
Filter
Memory
Field
Port C
Port B
Port A
12
12
12
12
3
SDC0 ... 11
BLN
NR422
CLASS
SQA0 ... 11
UEB10379
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