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參數(shù)資料
| 型號： | SDA9254-2 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
| 中文描述： | VIDEO DRAM, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 183K |
| 代理商： | SDA9254-2 |
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SDA 9254-2
Semiconductor Group
12
1998-01-16
Pin Definitions and Functions
Pin No.
Symbol
Input (I)
Output (O)
Function
15
.
.
18
21
22
27
28
SQA11
.
.
SQA8
SQA7
SQA6
SQA5
SQA4
O
.
.
.
.
.
.
O
Serial data output port A (luminance signal)
31
32
33
34
SQA3
.
.
SQA0
O
.
.
O
Serial data output port A (chrominance signal)
51
SCA
I
Serial clock input for port A
58
RA
I
Read transfer control input (latch A to shift register A)
26
OEA
I
Output enable input for port A
62
SCB
I
Serial clock input for port B and C
59
RB
I
Read transfer control input (latch B to shift register B)
23
OEDLO
I
Output enable input for delay line output
4
.
.
1
64
63
50
49
SDC11
.
.
SDC8
SDC7
SDC6
SDC5
SDC4
I
.
.
.
.
.
.
I
Serial data input port C (luminance signal)
48
47
46
45
SDC3
SDC2
SDC1
SDC0
I
I
I
I
Serial data input port C (chrominance signal)
60
WT
I
Write transfer control input (shift register C to latch C)
52
SAR
I
Serial row address input
53
SAC
I
Serial column address and mode control input
54
SCAD
I
Serial address clock input
55
RE
I
RAM-enable input (also latches the addresses)
5
6
CLASS0
CLASS1
I
I
Characteristic of the noise reduction filter
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