SCF5250 Data Sheet: Technical Data, Rev. 1.3 14 Freescale" />
參數(shù)資料
型號(hào)： SCF5250VM120
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 6/56頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT 120MHZ AUD 196-MAPBGA
產(chǎn)品變化通告： Product Discontinuation 24/Feb/2012
標(biāo)準(zhǔn)包裝： 126
系列： SCF52xx
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 120MHz
連通性： EBI/EMI，I²C，IDE，MMC，SPI，UART/USART
外圍設(shè)備： DMA，I²S，POR，串行音頻，WDT
輸入/輸出數(shù)： 57
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b
振蕩器型： 內(nèi)部
工作溫度： -20°C ~ 70°C
封裝/外殼： 196-LBGA
包裝： 托盤(pán)
SCF5250 Data Sheet: Technical Data, Rev. 1.3
14
Freescale Semiconductor
3.4
Chip Selects
There are three chip select outputs on the SCF5250 device. CS0/CS4 and CS1/QSPI_CS3/GPIO28 and
CS2 which is associated with the IDE interface read and write strobes - IDE-DIOR and IDE-DIOW.
CS0 and CS4 are multiplexed. The SCF5250 has the option to boot from an internal Boot ROM.
The function of the CS0/CS4 pin is determined by the boot mode. When the device is booted from internal
ROM, the internal ROM is accessed with CS0 (required for boot) and the CS0/CS4 pin is driven by CS4.
When the device is booted from external ROM / Flash, the CS0/CS4 pin is driven by CS0 and the internal
ROM is disabled.
The active low chip selects can be used to access asynchronous memories. The interface is glueless.
3.5
ISA Bus
The SCF5250 supports an ISA bus. Using the ISA bus protocol, reads and writes for one ISA bus
peripheral is possible. IDE-DIOR/GPIO31 and IDE-DIOW/GPIO32 are the read and write strobe. The
peripheral can insert wait states by pulling IDE-IORDY/GPIO33.
CS2 is associated with the IDE-DIOR and IDE-DIOW.
3.6
Bus Buffer Signals
As the SCF5250 has a complicated slave bus, which allows SDRAM, asynchronous memories, and ISA
peripherals on the bus, it may become necessary to introduce a buffer on the bus in certain applications.
The SCF5250 has a glueless interface to steer these bus buffers with two bus buffer output signals
BUFENB1/GPIO29 and BUFENB2/GPIO30.
3.7
I2C Module Signals
There are two I2C interfaces on this device as described in Table 4.
The I2C module acts as a two-wire, bidirectional serial interface between the SCF5250 processor and
peripherals with an I2C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When
devices connected to the I2C bus drive the bus, they will either drive logic-0 or high-impedance. This can
be accomplished with an open-drain output.
Table 4. I2C Module Signals
I2c Module Signal
Description
I2C Serial Clock
The SCL0/SDATA1_BS1/GPIO41 and SCL1/TXD1/GPIO10 bidirectional signals are the clock signal for
first and second I2C module operation. The I2C module controls this signal when the bus is in master
mode; all I2C devices drive this signal to synchronize I2C timing.
Signals are multiplexed
I2C Serial Data
The SDA0/SDATA3/GPIO42 and SDA1/RXD1/GPIO44 bidirectional signals are the data input/output for
the first and second serial I2C interface.
Signals are multiplexed
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參數(shù)描述
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