參數(shù)資料
型號: SC16IS752IBS,151
廠商: NXP Semiconductors
文件頁數(shù): 9/60頁
文件大?。?/td> 0K
描述: IC UART DUAL I2C/SPI 32-HVQFN
產(chǎn)品培訓(xùn)模塊: Bridge Solutions
Stand-Alone UARTs
I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 490
特點: 低電流
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱: 568-2236
935279288151
SC16IS752IBS-S
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
17 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Figure 10 shows the internal prescaler and baud rate generator circuitry.
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 11 shows the crystal clock circuit reference.
Fig 10. Prescaler and baud rate generator block diagram
Table 7.
Baud rates using a 1.8432 MHz crystal
Desired baud rate
(bit/s)
Divisor used to generate
16
clock
Percent error difference
between desired and actual
50
2304
0
75
1536
0
110
1047
0.026
134.5
857
0.058
150
768
0
300
384
0
600
192
0
1200
96
0
1800
64
0
2000
58
0.69
2400
48
0
3600
32
0
4800
24
0
7200
16
0
9600
12
0
19200
6
0
38400
3
0
56000
2
2.86
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
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