參數(shù)資料
型號(hào)： SC16IS752IBS,151
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 40/60頁(yè)
文件大?。?/td> 0K
描述： IC UART DUAL I2C/SPI 32-HVQFN
產(chǎn)品培訓(xùn)模塊： Bridge Solutions
Stand-Alone UARTs
I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： 低電流
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.5V, 3.3V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-HVQFN（5x5）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 828 (CN2011-ZH PDF)
配用： 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱： 568-2236
935279288151
SC16IS752IBS-S
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
45 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
14. Dynamic characteristics
[1]
A detailed description of the I2C-bus specification, with applications, is given in user manual UM10204: “I2C-bus specification and user
manual”. This may be found at www.nxp.com/documents/user_manual/UM10204.pdf.
[2]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
[3]
2 XTAL1 clock cycles or 3
s, whichever is less.
Table 37.
I2C-bus timing specifications[1]
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD =2.5 V 0.2 V, Tamb = 40 Cto+85 C; or VDD =3.3 V 0.3 V, Tamb = 40 Cto +95 C; VIL and VIH refer to input
voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
bus free time between a STOP and START
condition
4.7
-
1.3
-
s
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
s
tSU;STA
set-up time for a repeated START condition
4.7
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4.7
-
0.6
-
s
tHD;DAT
data hold time
0
-
0
-
ns
tVD;ACK
data valid acknowledge time
-
0.6
-
0.6
s
tVD;DAT
data valid time
SCL LOW to
data out valid
-
0.6
-
0.6
ns
tSU;DAT
data set-up time
250
-
150
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
s
tf
fall time of both SDA and SCL signals
-
300
-
300
ns
tr
rise time of both SDA and SCL signals
-
1000
-
300
ns
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
td1
I2C-bus GPIO output valid time
0.5
-
0.5
-
s
td2
I2C-bus modem input interrupt valid time
0.2
-
0.2
-
s
td3
I2C-bus modem input interrupt clear time
0.2
-
0.2
-
s
td4
I2C input pin interrupt valid time
0.2
-
0.2
-
s
td5
I2C input pin interrupt clear time
0.2
-
0.2
-
s
td6
I2C-bus receive interrupt valid time
0.2
-
0.2
-
s
td7
I2C-bus receive interrupt clear time
0.2
-
0.2
-
s
td8
I2C-bus transmit interrupt clear time
1.0
-
0.5
-
s
td15
SCL delay after reset
3-
3
-
s
tw(rst)
reset pulse width
3
-
3
-
s
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SC16IS752IPW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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