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| 型號(hào)： | SC16IS752IBS,151 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 6/60頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL I2C/SPI 32-HVQFN |
| 產(chǎn)品培訓(xùn)模塊： | Bridge Solutions Stand-Alone UARTs I²C Bus Fundamentals |
| 特色產(chǎn)品： | NXP - I2C Interface |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 特點(diǎn)： | 低電流 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.5V, 3.3V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-HVQFN（5x5） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 828 (CN2011-ZH PDF) |
| 配用： | 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART |
| 其它名稱： | 568-2236 935279288151 SC16IS752IBS-S |
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SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
14 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.5 Interrupts
The SC16IS752/SC16IS762 has interrupt generation and prioritization (seven prioritized
levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable
each of the seven types of interrupts and the IRQ signal in response to an interrupt
generation. When an interrupt is generated, the IIR indicates that an interrupt is pending
and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt
control functions.
It is important to note that for the framing error, parity error, and break conditions, Line
Status Register bit 7 (LSR[7]) generates the interrupt. LSR[7] is set when there is an error
anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in
the FIFO. LSR[4:2] always represent the error status for the received character at the top
of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
Table 6.
Summary of interrupt control functions
IIR[5:0]
Priority
level
Interrupt type
Interrupt source
00 0001
none
00 0110
1
receiver line status
Overrun Error (OE), Framing Error (FE), Parity Error
(PE), or Break Interrupt (BI) errors occur in
characters in the RX FIFO
00 1100
2
RX time-out
stale data in RX FIFO
00 0100
2
RHR interrupt
receive data ready (FIFO disable) or
RX FIFO above trigger level (FIFO enable)
00 0010
3
THR interrupt
transmit FIFO empty (FIFO disable) or
TX FIFO passes above trigger level (FIFO enable)
00 0000
4
modem status
change of state of modem input pins
11 0000
5
I/O pins
input pins change of state
01 0000
6
Xoff interrupt
receive Xoff character(s)/special character
10 0000
7
CTS, RTS
RTS pin or CTS pin change state from active (LOW)
to inactive (HIGH)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16IS752IBS-F | 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE W/IRDA AND GPIO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS752IPW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
| SC16IS752IPW,112 | 功能描述:UART 接口集成電路 UART DUAL 12C/SPI RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS752IPW,128 | 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS752IPW112 | 制造商:NXP Semiconductors 功能描述:IC DUAL UART FIFO 5MBPS 3.6V TSSOP28 |
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