參數(shù)資料
型號: SC16IS752IBS,151
廠商: NXP Semiconductors
文件頁數(shù): 52/60頁
文件大?。?/td> 0K
描述: IC UART DUAL I2C/SPI 32-HVQFN
產(chǎn)品培訓(xùn)模塊: Bridge Solutions
Stand-Alone UARTs
I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 490
特點: 低電流
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱: 568-2236
935279288151
SC16IS752IBS-S
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
56 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Appendix
18.1 Errata for Rev. E added 12 August 2011
18.1.1 IrDA wake-up
In Rev. D, the UART cannot wake up through RX pin once the UART is put to sleep by the
host.
18.1.2 Clearing of RX FIFO overflow
In Rev. D, once the receive FIFO overflows, the receive FIFO cannot be cleared with FIFO
reset command if the UART is continuously receiving data.
18.1.3 Interrupt priority encoder
When the edge of the IOR signal (an internal signal that reads IIR register) comes close to
the X1 clock that generates the interrupt, the value of the Interrupt Indication Register (IIR)
might not be correct. This issue might occur if the X1 clock is very slow and the host read
operation is very fast in response to the interrupt from the UART.
18.1.4 Time-out interrupt
If the host reads the receive FIFO at the at the same time as a time-out interrupt condition
happens, the host might read 0xCC (time-out) in the Interrupt Indication Register (IIR), but
bit 0 of the Line Status Register (LSR) is not set (means there is not data in the
receive FIFO). This is a conflict of the receive FIFO status when IIR = 0xCC (time-out), it
indicates that there are data in the receive FIFO, but LSR bit 0 = 0 indicates otherwise.
MSL: Moisture Sensitivity Level
Fig 39. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
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