參數(shù)資料
型號(hào)： SB80L186EC13
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 13 MHz, MICROPROCESSOR, PQFP100
封裝： SHRINK, QFP-100
文件頁(yè)數(shù)： 2/57頁(yè)
文件大?。?/td> 1573K
代理商： SB80L186EC13
80C186EC188EC 80L186EC188EC
Table 2 Pin Descriptions
Pin Name
Pin
Input
Output
Pin Description
Type
States
VCC
P
POWER a
5V g10% power supply connection
VSS
G
GROUND
CLKIN
I
A(E)
CLocK INput
is the external clock input An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN For
crystal operation CLKIN (along with OSCOUT) are the
crystal connections to an internal Pierce oscillator
OSCOUT
O
H(Q)
OSCillator OUTput
is only used when using a crystal to
generate the internal clock OSCOUT (along with CLKIN)
R(Q)
are the crystal connections to an internal Pierce oscillator
I(Q)
This pin can not be used as 2X clock output for non-
P(X)
crystal applications (ie this pin is not connected for non-
crystal applications)
CLKOUT
O
H(Q)
CLocK OUTput
provides a timing reference for inputs and
outputs of the processor and is one-half the input clock
R(Q)
(CLKIN) frequency CLKOUT has a 50% duty cycle and
I(Q)
transitions every falling edge of CLKIN
P(X)
RESIN
I
A(L)
RESet IN
causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state
All pins will be driven to a known state and RESOUT will
also be driven active The rising edge (low-to-high)
transition synchronizes CLKOUT with CLKIN before the
processor begins fetching opcodes at memory location
0FFFF0H
RESOUT
O
H(0)
RESet OUTput
that indicates the processor is currently in
the reset state RESOUT will remain active as long as
R(1)
RESIN remains active
I(0)
P(0)
PDTMR
IO
A(L)
H(WH)
Power-Down TiMeR
pin (normally connected to an
external capacitor) that determines the amount of time the
R(Z)
processors waits after an exit from Powerdown before
P(WH)
resuming normal operation The duration of time required
I(WH)
will depend on the startup characteristics of the crystal
oscillator
NMI
I
A(E)
Non-Maskable Interrupt
input causes a TYPE-2 interrupt
to be serviced by the CPU NMI is latched internally
TEST BUSY
I
A(E)
TEST
is used during the execution of the WAIT instruction
to suspend CPU operation until the pin is sampled active
(TEST)
(LOW) TEST is alternately known as BUSY when
interfacing with an 80C187 numerics coprocessor
(80C186EC only)
A19S6ONCE
IO
A(L)
H(Z)
This pin drives address bit 19 during the address phase of
the bus cycle During T2 and T3 this pin functions as
R(WH)
status bit 6 S6 is low to indicate CPU bus cycles and high
I(0)
to indicate DMA or refresh bus cycles During a processor
P(0)
reset (RESIN active) this pin becomes the ONCE input
pin Holding this pin low during reset will force the part into
ONCE Mode
NOTE
Pin names in parentheses apply to the 80C188EC80L188EC
10
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SB80L186EC-13 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
SB80L186EC16 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
SB80L186EC20 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
SB80L186EC25 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
SB80L188EA-13 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
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