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| 型號(hào)： | SAX-XC878M-16FFI3V3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 24 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 128/141頁(yè) |
| 文件大?。?/td> | 2385K |
| 代理商： | SAX-XC878M-16FFI3V3 |
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XC878CLM
Functional Description
Data Sheet
80
V1.1, 2009-08
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC878 system reset. Hence, routine service of the WDT confirms
that the system is functioning properly. This ensures that an accidental malfunction of
the XC878 will be aborted in a user-specified time period.
In debug mode, the WDT is default suspended and stops counting. Therefore, there is
no need to refresh the WDT during debugging.
Features
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of
f
PCLK/2 or fPCLK/128
Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of
f
PCLK/2 or fPCLK/128. This 16-bit
timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be
preset to a user-programmable value via a watchdog service access in order to modify
the watchdog expire time period. The lower 8 bits are reset on each service access.
Figure 23 shows the block diagram of the WDT unit.
Figure 23
WDT Block Diagram
WDTREL
MUX
WDT Low Byte
1:2
Clear
WDT
Control
1:128
WDT High Byte
FNMIWDT
WDTIN
f
PCLK
Logic
ENWDT
ENWDT_P
WDTRST
Overflow/Time-out Control &
Window-boundary control
WDTWINB
.
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