
XC878CLM
Functional Description
Data Sheet
74
V1.1, 2009-08
not be bypassed for this PLL mode. The PLL mode is used during normal system
operation.
(3.2)
System Frequency Selection
For the XC878, the value of NF, NR and OD can be selected by bits NDIV, PDIV and
KDIV respectively for different oscillator inputs inorder to obtain the required fsys. But the
combination of these factors must fulfill the following condition:
100 MHz < fVCO <175 MHz
800 KHz < fOSC / (2 * NR) < 8 MHz
Table 25 provides examples on how the typical system frequency of fsys = 144 MHz
and maximum frequency of 160 MHz (CPU clock = 26.67 MHz)can be obtained for the
different oscillator sources.
3.8.1
Recommended External Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 2 MHz to
20 MHz. Additionally, it is necessary to have two load capacitances
C
X1 and CX2, and
depending on the crystal type, a series resistor
R
X2, to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry.
R
Q values are typically specified by the crystal vendor. An
external feedback resistor
R
f is also required in the external oscillator circuitry. The exact
values and related operating range are dependent on the crystal frequency and have to
be determined and optimized together with the crystal vendor using the negative
Table 25
System frequency (
f
sys =144 MHz)
Oscillator
fosc
N
P
K
fsys
On-chip
4 MHz
72
2
1
144 MHz
4 MHz
80
2
1
160 MHz
External
8 MHz
72
4
1
144 MHz
6 MHz
72
3
1
144 MHz
4 MHz
72
2
1
144 MHz
OD
x
NR
NF
x
f
OSC
SYS =