參數(shù)資料
型號(hào): SAL-XC866L-4FRA
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 75 MHz, MICROCONTROLLER, PDSO38
封裝: GREEN, PLASTIC, TSSOP-38
文件頁(yè)數(shù): 84/113頁(yè)
文件大小: 2289K
代理商: SAL-XC866L-4FRA
SAL-XC866
Functional Description
PRELIMINARY
Data Sheet
68
V1.0, 2011-02
3.11.1
Baud-Rate Generator
The baud-rate generator is based on a programmable 8-bit reload value, and includes
divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud
rates based on its input clock fPCLK, see Figure 28.
Figure 28
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the
output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (fBR) value is dependent on the following parameters:
Input clock fPCLK
Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON
Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
FDSTEP
1
FDM
Adder
FDRES
FDEN&FDM
clk
Fractional Divider
Prescaler
NDOV
‘0’
FDEN
00
01
10
11
10
01
00
0
1
(overflow)
0
f
BR
8-Bit Baud Rate Timer
8-Bit Reload Value
R
0
1
f
DIV
f
DIV
f
PCLK
f
MOD
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