參數(shù)資料
型號： SAL-XC866L-4FRA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 75 MHz, MICROCONTROLLER, PDSO38
封裝： GREEN, PLASTIC, TSSOP-38
文件頁數(shù)： 41/113頁
文件大?。?/td> 2289K
代理商： SAL-XC866L-4FRA
SAL-XC866
Functional Description
PRELIMINARY
Data Sheet
29
V1.0, 2011-02
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 8
Port Register Overview
Addr
Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
B2H
PORT_PAGE
Reset: 00H
Page Register for PORT
Bit Field
OP
STNR
0
PAGE
Type
w
r
rwh
RMAP = 0, Page 0
80H
P0_DATA
Reset: 00H
P0 Data Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rwh
86H
P0_DIR
Reset: 00H
P0 Direction Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
90H
P1_DATA
Reset: 00H
P1 Data Register
Bit Field
P7
P6
P5
0
P1
P0
Type
rwh
r
rwh
91H
P1_DIR
Reset: 00H
P1 Direction Register
Bit Field
P7
P6
P5
0
P1
P0
Type
rw
r
rw
A0H
P2_DATA
Reset: 00H
P2 Data Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rwh
A1H
P2_DIR
Reset: 00H
P2 Direction Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
B0H
P3_DATA
Reset: 00H
P3 Data Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rwh
B1H
P3_DIR
Reset: 00H
P3 Direction Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
RMAP = 0, Page 1
80H
P0_PUDSEL
Reset: FFH
P0 Pull-Up/Pull-Down Select Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
86H
P0_PUDEN
Reset: C4H
P0 Pull-Up/Pull-Down Enable Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
90H
P1_PUDSEL
Reset: FFH
P1 Pull-Up/Pull-Down Select Register
Bit Field
P7
P6
P5
0
P1
P0
Type
rw
r
rw
91H
P1_PUDEN
Reset: FFH
P1 Pull-Up/Pull-Down Enable Register
Bit Field
P7
P6
P5
0
P1
P0
Type
rw
r
rw
A0H
P2_PUDSEL
Reset: FFH
P2 Pull-Up/Pull-Down Select Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
A1H
P2_PUDEN
Reset: 00H
P2 Pull-Up/Pull-Down Enable Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
B0H
P3_PUDSEL
Reset: BFH
P3 Pull-Up/Pull-Down Select Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
B1H
P3_PUDEN
Reset: 40H
P3 Pull-Up/Pull-Down Enable Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
RMAP = 0, Page 2
80H
P0_ALTSEL0
Reset: 00H
P0 Alternate Select 0 Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
86H
P0_ALTSEL1
Reset: 00H
P0 Alternate Select 1 Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
90H
P1_ALTSEL0
Reset: 00H
P1 Alternate Select 0 Register
Bit Field
P7
P6
P5
0
P1
P0
Type
rw
r
rw
91H
P1_ALTSEL1
Reset: 00H
P1 Alternate Select 1 Register
Bit Field
P7
P6
P5
0
P1
P0
Type
rw
r
rw
B0H
P3_ALTSEL0
Reset: 00H
P3 Alternate Select 0 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
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