參數(shù)資料
型號(hào): SAL-XC866L-4FRA
廠商: INFINEON TECHNOLOGIES AG
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 75 MHz, MICROCONTROLLER, PDSO38
封裝: GREEN, PLASTIC, TSSOP-38
文件頁(yè)數(shù): 42/113頁(yè)
文件大小: 2289K
代理商: SAL-XC866L-4FRA
SAL-XC866
Functional Description
PRELIMINARY
Data Sheet
30
V1.0, 2011-02
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
B1H
P3_ALTSEL1
Reset: 00H
P3 Alternate Select 1 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
RMAP = 0, Page 3
80H
P0_OD
Reset: 00H
P0 Open Drain Control Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
90H
P1_OD
Reset: 00H
P1 Open Drain Control Register
Bit Field
P7
P6
P5
0
P1
P0
Type
rw
r
rw
B0H
P3_OD
Reset: 00H
P3 Open Drain Control Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
Table 9
ADC Register Overview
Addr
Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D1H
ADC_PAGE
Reset: 00H
Page Register for ADC
Bit Field
OP
STNR
0
PAGE
Type
w
r
rwh
RMAP = 0, Page 0
CAH
ADC_GLOBCTR
Reset: 30H
Global Control Register
Bit Field
ANON
DW
CTC
0
Type
rw
r
CBH
ADC_GLOBSTR
Reset: 00H
Global Status Register
Bit Field
0
CHNR
0
SAM
PLE
BUSY
Type
r
rh
r
rh
CCH
ADC_PRAR
Reset: 00H
Priority and Arbitration Register
Bit Field
ASEN1 ASEN0
0
ARBM
CSM1 PRIO1 CSM0 PRIO0
Type
rw
r
rw
CDH
ADC_LCBR
Reset: B7H
Limit Check Boundary Register
Bit Field
BOUND1
BOUND0
Type
rw
CEH
ADC_INPCR0
Reset: 00H
Input Class Register 0
Bit Field
STC
Type
rw
CFH
ADC_ETRCR
Reset: 00H
External Trigger Control Register
Bit Field
SYNEN
1
SYNEN
0
ETRSEL1
ETRSEL0
Type
rw
RMAP = 0, Page 1
CAH
ADC_CHCTR0
Reset: 00H
Channel Control Register 0
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
CBH
ADC_CHCTR1
Reset: 00H
Channel Control Register 1
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
CCH
ADC_CHCTR2
Reset: 00H
Channel Control Register 2
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
CDH
ADC_CHCTR3
Reset: 00H
Channel Control Register 3
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
CEH
ADC_CHCTR4
Reset: 00H
Channel Control Register 4
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
CFH
ADC_CHCTR5
Reset: 00H
Channel Control Register 5
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
D2H
ADC_CHCTR6
Reset: 00H
Channel Control Register 6
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
D3H
ADC_CHCTR7
Reset: 00H
Channel Control Register 7
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
RMAP = 0, Page 2
Table 8
Port Register Overview (cont’d)
Addr
Register Name
Bit
7
6
5
4
3
2
1
0
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