參數(shù)資料
型號： SAK-XC2765X-72F80LAA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 87/123頁
文件大?。?/td> 1000K
代理商： SAK-XC2765X-72F80LAA
XC2765X
XC2000 Family Derivatives / Base Line
Functional Description
Data Sheet
66
V2.0, 2009-03
3.18
Parallel Ports
The XC2765X provides up to 76 I/O lines which are organized into 7 input/output ports
and 2 input ports. All port lines are bit-addressable, and all input/output lines can be
individually (bit-wise) configured via port control registers. This configuration selects the
direction (input/output), push/pull or open-drain operation, activation of pull devices, and
edge characteristics (shape) and driver characteristics (output current) of the port
drivers. The I/O ports are true bidirectional ports which are switched to high impedance
state when configured as inputs. During the internal reset, all port pins are configured as
inputs without pull devices active.
All port lines have alternate input or output functions associated with them. These
alternate functions can be programmed to be assigned to various port pins to support the
best utilization for a given application. For this reason, certain functions appear several
times in Table 10.
All port lines that are not used for alternate functions may be used as general purpose
I/O lines.
Table 10
Summary of the XC2765X’s Ports
Port
Width
I/O
Connected Modules
P0
8
I/O
EBC (A7...A0), CCU6, USIC, CAN
P1
8
I/O
EBC (A15...A8), CCU6, USIC
P2
14
I/O
EBC (READY, BHE, A23...A16, AD15...AD13, D15...D13),
CAN, CC2, GPT12E, USIC, DAP/JTAG
P4
4
I/O
EBC (CS3...CS0), CC2, CAN, GPT12E, USIC
P5
11
I
Analog Inputs, CCU6, DAP/JTAG, GPT12E, CAN
P6
3
I/O
ADC, CAN, GPT12E
P7
5
I/O
CAN, GPT12E, SCU, DAP/JTAG, CCU6, ADC, USIC
P10
16
I/O
EBC(ALE, RD, WR, AD12...AD0, D12...D0), CCU6, USIC,
DAP/JTAG, CAN
P15
5
I
Analog Inputs, GPT12E
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