參數(shù)資料
型號(hào)： SAK-XC2765X-72F80LAA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 54/123頁
文件大?。?/td> 1000K
代理商： SAK-XC2765X-72F80LAA
XC2765X
XC2000 Family Derivatives / Base Line
Functional Description
Data Sheet
36
V2.0, 2009-03
3.1
Memory Subsystem and Organization
The memory space of the XC2765X is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Table 6
XC2765X Memory Map
Address Area
Start Loc. End Loc.
Area Size1)
Notes
IMB register space
FF’FF00H
FF’FFFFH
256 Bytes
–
Reserved (Access trap) F0’0000H
FF’FEFFH <1 Mbyte
Minus IMB registers
Reserved for EPSRAM E8’8000H
EF’FFFFH 480 Kbytes
Mirrors EPSRAM
Emulated PSRAM
E8’0000H
E8’7FFFH
32 Kbytes
Flash timing
Reserved for PSRAM
E0’8000H
E7’FFFFH
480 Kbytes
Mirrors PSRAM
Program SRAM
E0’0000H
E0’7FFFH
32 Kbytes
Maximum speed
Reserved for Flash
CD’0000H
DF’FFFFH <1.25 Mbytes –
Program Flash 3
CC’0000H
CC’FFFFH 64 Kbytes
–
Program Flash 2
C8’0000H
CB’FFFFH 256 Kbytes
–
Program Flash 1
C4’0000H
C7’FFFFH 256 Kbytes
–
Program Flash 0
C0’0000H
C3’FFFFH 256 Kbytes
2)
External memory area
40’0000H
BF’FFFFH 8 Mbytes
–
Available Ext. IO area3) 21’0000H
3F’FFFFH
< 2 Mbytes
Minus USIC/CAN
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