參數(shù)資料
型號： SAK-XC2765X-72F80LAA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 76/123頁
文件大小： 1000K
代理商： SAK-XC2765X-72F80LAA
XC2765X
XC2000 Family Derivatives / Base Line
Functional Description
Data Sheet
56
V2.0, 2009-03
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
counting direction (up/down) for each timer can be programmed by software or altered
dynamically with an external signal on a port pin (TxEUD1)). Concatenation of the timers
is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2
timers and to initiate a reload from the CAPREL register.
The CAPREL register can capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared
after the capture procedure. This allows the XC2765X to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of
GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
1) Exception: T5EUD is not connected to a pin.
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