參數(shù)資料
型號(hào)： SAK-XC2765X-72F80LAA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 67/123頁
文件大?。?/td> 1000K
代理商： SAK-XC2765X-72F80LAA
XC2765X
XC2000 Family Derivatives / Base Line
Functional Description
Data Sheet
48
V2.0, 2009-03
The XC2765X includes an excellent mechanism to identify and process exceptions or
error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware
trap causes an immediate non-maskable system reaction similar to a standard interrupt
service (branching to a dedicated vector table location). The occurrence of a hardware
trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-
priority trap service is in progress, a hardware trap will interrupt any ongoing program
execution. In turn, hardware trap services can normally not be interrupted by standard
or PEC interrupts.
Table 8 shows all possible exceptions or error conditions that can arise during runtime:
Table 8
Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Location1)
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Trap
Number
Trap
Priority
Reset Functions
–
RESET
xx’0000H
00H
III
Class A Hardware Traps:
System Request 0
Stack Overflow
Stack Underflow
Software Break
SR0
STKOF
STKUF
SOFTBRK
SR0TRAP
STOTRAP
STUTRAP
SBRKTRAP
xx’0008H
xx’0010H
xx’0018H
xx’0020H
02H
04H
06H
08H
II
Class B Hardware Traps:
System Request 1
Memory Protection
Undefined Opcode
Memory Access Error
Protected Instruction
Fault
Illegal Word Operand
Access
SR1
MPR/W/X
UNDOPC
ACER
PRTFLT
ILLOPA
BTRAP
xx’0028H
0AH
I
Reserved
–
[2CH - 3CH][0BH -
0FH]
–
Software Traps:
TRAP Instruction
––
Any
[xx’0000H -
xx’01FCH]
in steps of
4H
Any
[00H -
7FH]
Current
CPU
Priority
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