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參數(shù)資料
| 型號(hào)： | SAF-TC1910-LEBBA |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC MICROCONTROLLER, PBGA208 |
| 封裝： | PLASTIC, LBGA-208 |
| 文件頁(yè)數(shù)： | 21/68頁(yè) |
| 文件大?。?/td> | 2700K |
| 代理商： | SAF-TC1910-LEBBA |
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TC1910
Data Sheet
24
V 1.0, 2003-10
PRELIMINARY
Timer Unit (GPTU)
Figure 8 shows a global view of all functional blocks of the GPTU module.
Figure 8
General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as
event timing, event counting, and event recording. The GPTU communicates with the
external world via eight inputs and eight outputs.
The three timers of the GPTU module T0, T1, and T2, can operate independently from
each other, or can be combined:
General Features:
All timers are 32-bit precision timers with a maximum input frequency of fGPTU/2.
Events generated in T0 or T1 can be used to trigger actions in T2
Timer overflow or underflow in T2 can be used to clock either T0 or T1
T0 and T1 can be concatenated to form one 64-bit timer
Features of T0 and T1:
Each timer has a dedicated 32-bit reload register with automatic reload on overflow
Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload
registers
Overflow signals can be selected to generate service requests, pin output signals, and
T2 trigger events
Two input pins can determine a count option
M C B 05052_m odified
Clo c k
Con tro l
A ddress
D e coder
Interru p t
Con tro l
SR 1
SR 2
f
GP T U
SR 3
SR 0
GP T U
M odule
(K ernel)
Po rt
Co ntro l
P 0.1 / G P T 1
SR 7
SR 6
SR 5
SR 4
IN 1
IN 2
IN 3
IN 0
IN 7
IN 6
IN 5
IN 4
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
IO 1
IO 7
IO 0
P 0.0 / G P T 0
IO 2
P 0.2 / G P T 2
IO 3
P 0.3 / G P T 3
P 0.4 / G P T 4
IO 4
IO 5
P 0.5 / G P T 5
IO 6
P 0.6 / G P T 6
P 0 .7 / G P T 7
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