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參數(shù)資料
| 型號(hào)： | SAF-TC1910-LEBBA |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC MICROCONTROLLER, PBGA208 |
| 封裝： | PLASTIC, LBGA-208 |
| 文件頁(yè)數(shù)： | 11/68頁(yè) |
| 文件大?。?/td> | 2700K |
| 代理商： | SAF-TC1910-LEBBA |
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TC1910
PRELIMINARY
Data Sheet
15
V 1.0, 2003-10
System Control Unit (SCU)
The System Control Unit of the TC1910 basically handles all system control tasks. All
these system functions are tightly coupled and therefore they are handled physically by
one unit, the SCU. The system tasks of the SCU are:
Clock Generation and Control
Reset control
Power Management control and wake-up
Watchdog timer
Device identification
Standby SRAM control
External interrupt capability (8 sources)
System timer (STM)
The System Timer is designed for global system timing applications requiring both high
precision and long range. It is used by the CPU for software operating system issues.
Features:
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Driven by clock,
f STM (normally identical with the system clock).
Counting begins at power-on reset
Continuous operation is not affected by any reset condition except power-on reset
External Bus Interface (EBU_LMB)
EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1910 and also to the
FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus.
Any LMB masters thus can access external memories or devices through EBU_LMB.
Currently the maximum length of the bursts are according to the size of program and
data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8-
bit, 16-bit and 32-bit wide access.
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