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參數(shù)資料
| 型號： | SAF-TC1910-LEBBA |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC MICROCONTROLLER, PBGA208 |
| 封裝： | PLASTIC, LBGA-208 |
| 文件頁數(shù)： | 19/68頁 |
| 文件大?。?/td> | 2700K |
| 代理商： | SAF-TC1910-LEBBA |
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TC1910
Data Sheet
22
V 1.0, 2003-10
PRELIMINARY
High-Speed Synchronous Serial Interface (SSC)
The High Speed Synchronous Serial Interface SSC provides serial communication
between microcontrollers, microprocessors or external peripherals. The SSC supports
full-duplex and half-duplex synchronous communication up to 25 MBaud (@ 50 MHz
module clock). The serial clock signal can be generated by the SSC itself (master mode)
or be received from an external master (slave mode). Data width, shift direction, clock
polarity and phase are programmable. This allows communication with SPI-compatible
devices. Transmission and reception of data are double-buffered. A 16-bit baud rate
generator provides the SSC with a separate serial clock signal.
Features:
Master and slave mode operation
– Full-duplex or half-duplex operation
Flexible data format
– Programmable number of data bits : 2 to 16 bit
– Programmable shift direction : LSB or MSB shift first
– Programmable clock polarity : idle low or high state for the shift clock
– Programmable clock/data phase : data shift with leading or trailing edge of SCLK
Maximum baudrate: 25 MBaud in Master, 12.5 in Slave mode (@ 50 MHz module
clock)
Interrupt generation
– on a transmitter empty condition
– on a receiver full condition
– on an error condition (receive, phase, baudrate, transmit error)
Three pin interface
Figure 7
General Block Diagram of the SSC Interface
M C B 04505_m od
Clo c k
Con tro l
A ddress
De c o de r
Interru p t
Con tro l
f
hw _c lk
SS C
M odule
(K erne l)
Po rt
C ontro l
MR S T
RX D
TXD
Ma
s
te
r
RX D
TXD
Sla
v
e
Sla v e
Ma s te r
SC
L
K
MT S R
SC L K
EIR
RIR
TIR
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