參數(shù)資料
型號： SAF-TC1910-LEBBA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 66 MHz, RISC MICROCONTROLLER, PBGA208
封裝： PLASTIC, LBGA-208
文件頁數(shù)： 13/68頁
文件大?。?/td> 2700K
代理商： SAF-TC1910-LEBBA
TC1910
Data Sheet
16
V 1.0, 2003-10
PRELIMINARY
Figure 4
EBU_LMB block diagram
Features supported in EBU_LMB:
Local Memory Bus (LMB 64-bit) support.
External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4.
Highly programmable access parameters.
Intel-style and Motorola-style peripheral/device support.
SDRAM support (burst access, multibanking, precharge, refresh).
16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices.
Burst flash support.
Multiplexed access (address & data on the same bus) when DRAM is not present on
the External Bus.
Data Buffering: Code Prefetch Buffer, Read/Write Buffer.
External master arbitration (compatible to C166 and other TriCore devices).
8 programmable address regions (1 dedicated for emulator).
Little-Endian and Big-Endian support.
CSglb signal, dedicated pin, bit programmable to combine one or more CS lines, for
buffer control.
RMW signal reflecting a read-modify-write action.
Signal for controlling data flow of slow-memory buffer.
Slave unit for external (off-chip) master to access devices on the FPI bus.
Master unit for FPI master to access external (off-chip) devices.
Data Mover Engine.
SD RA M
B u ffe r
XBC
EBU _ L M B
XM I
FPI Bu s 3 2 -b it
Ex
te
rnal
Bu
s
32
-bit
LM B Bu s 6 4 -b it
DM E
EBU L3045_L
Ex te rn a l Bu s U n it
Ex te rn al
Ma s te r
Slow er
D e vices
50 M H z
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