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參數(shù)資料
| 型號(hào)： | SAF-TC11IB-64D96EBC |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 96 MHz, RISC MICROCONTROLLER, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁(yè)數(shù)： | 7/110頁(yè) |
| 文件大?。?/td> | 1303K |
| 代理商： | SAF-TC11IB-64D96EBC |
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TC11IB
Data Sheet
100
V2.4, 2004-06
PCI 3.3V Timing Parameters
(
Operating Conditions apply; CL = 10 pF)
Parameter
Symbol
Min.
Max.
Units
Notes
CLK to signal valid delay
- bused signals
tVAL
211
ns
1) 2) 3)
1) Refer to Figure 43.
2) Minimum times are evaluated with same load used for slew rate measurement (as shown in Figure 41).
Maximum times are evaluated with the load circuits as illustrated in Figure 45.
3) REQ and GNT are point to point signals and have different output valid delay and input setup times compared
to bused signals. GNT has a setup of 10 and REQ has a setup of 12. All other signals are bused.
CLK to signal valid delay
- point to point
tVAL(PTP) 212
ns
1) 2) 3)
Float to active delay
tON
2ns
1) 4)
4) For purposes of Active/Float timing measurements, the Hi-Z or "OFF" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
Active to Float delay
tOFF
28
ns
1) 4)
Input setup time to CLK
- bused signals
tSU
7ns
3) 5) 6)
5) Refer to Figure 44.
6) Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the
same time.
Input setup time to CLK
- point to point
tSU(PTP) 10, 12
ns
3) 5)
Input hold time from CLK
tH
0ns
5)
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