參數(shù)資料
型號(hào)： SAF-TC11IB-64D96EBC
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 96 MHz, RISC MICROCONTROLLER, PBGA388
封裝： PLASTIC, BGA-388
文件頁(yè)數(shù)： 59/110頁(yè)
文件大?。?/td> 1303K
代理商： SAF-TC11IB-64D96EBC
TC11IB
Data Sheet
48
V2.4, 2004-06
On-Chip FPI Bus
The FPI Bus interconnects the functional units of the TC11IB, such as the PCP and on-
chip peripheral components. The FPI Bus is designed to be quick to acquire by on-chip
functional units, and quick to transfer data. The low setup overhead of the FPI Bus
access protocol guarantees fast FPI Bus acquisition, which is required for time-critical
applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak
transfer rate of up to 800 MBytes/s can be achieved with a 100 MHz bus clock and 32-
bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate
at close to its peak bandwidth. Via External Bus Unit (EBU), FPI Bus also interconnects
the external components to TC11IB.
There are two FPI buses in TC11IB, Fast FPI Bus and Slow FPI Bus. In order to improve
the system performance, the peripherals are splitted into two FPI buses based on their
performance. The fast FPI bus runs at a speed of 96 MHz where most of the high
performance peripheral like ComDRAM, PCI-FPI, Ethernet Controller, LFI etc. are
connected. The slow FPI bus runs at half speed of its fast counter part. And it is used to
connect some standard peripherals. There is a FPI-FPI bridge between them to transfer
data. Each of FPI buses has its own Bus Control Unit (BCU).
Features
Supports multiple bus masters
Supports demultiplexed address/data operation
Address bus up to 32 bits and data buses are 64 bits wide
Data transfer types include 8-, 16-, 32- and 64 bit sizes
Supports Burst transfer
Single- and multiple-data transfers per bus acquisition cycle
Designed to minimize EMI and power consumption
Controlled by an Bus Control Unit (BCU)
– Arbitration of FPI Bus master requests
– Handling of bus error.
FFI-Bridge Features
Supports Single/Block* Data Read/Write Transactions (8/16/32 Bit)
Supports FPI- Read Modify Write Transactions (RMW)
Internal FIFO Interfaces between FPI master and FPI slave.
Optimized for FPI-Bus frequency ratios 2:1
Special Retry/Abort functionality
Note: Block Transaction support depends on generic settings and the depth of the
bridge internal read- and write data buffer.
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