參數(shù)資料
型號： SAF-TC1130-L150EBGREEN
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 150 MHz, MICROCONTROLLER, PBGA208
封裝： GREEN, PLASTIC, LBGA-208
文件頁數(shù)： 89/117頁
文件大?。?/td> 1726K
代理商： SAF-TC1130-L150EBGREEN
TC1130
Functional Description
Data Sheet
67
V1.0, 2005-02
Advance Information
3.24
Clock Generation Unit
The Clock Generation Unit (CGU) allows a flexible clock generation for TC1130. The
power consumption is indirectly proportional to the frequency, whereas the performance
of the microcontroller is directly proportional to the frequency. During user program
execution, the frequency can be programmed for an optimal ratio between performance
and power consumption. Therefore, the power consumption can be adapted to the actual
application state.
Features:
The Clock Generation Unit serves several purposes:
PLL feature for multiplying clock source by different factors
Direct Drive for direct clock input
Comfortable state machine for secure switching between basic PLL, direct, or
prescaler operation
Sleep and Power-down mode support
USB Clock source and control
The Clock Generation Unit in the TC1130, shown in Figure 3-16, consists of an oscillator
circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it looses the lock on the external clock.
In general, the Clock Generation Unit (CGU) is controlled through the System Control
Unit (SCU) module of the TC1130.
Figure 3-16 Clock Generation Unit Block Diagram
1
>
MCA04940mod
Oscillator
Circuit
XTAL1
XTAL2
f
OSC
Phase
Detect.
VCO
N
Divider
PLL
f
VCO
1
0
1:1/1:2
Divider
f
SYS
Lock
Detector
OSCR
PLL_
LOCK
NDIV
[6:0]
VCO_
BYPASS
KDIV
[3:0]
PLL_
BYPASS
System Control Unit
SCU
Register PLL_CLC
MUX
K:1/K:2
Divider
VCO_
SEL[1:0]
f
CPU
SYS
FSL
Clock Generation Unit
CGU
P
Divi-
der
Osc.
Run
Detect.
PDIV
[2:0]
OSC
DISC
P4.0/
USBCLK
Divider
MUX
f
USB
Register SCU_CON
USBC
LDIV
USBC
LSEL
Register OSC_CON
MOSC
OGC
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