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參數(shù)資料
| 型號： | SAF-TC1130-L150EBGREEN |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 150 MHz, MICROCONTROLLER, PBGA208 |
| 封裝： | GREEN, PLASTIC, LBGA-208 |
| 文件頁數(shù)： | 109/117頁 |
| 文件大?。?/td> | 1726K |
| 代理商： | SAF-TC1130-L150EBGREEN |
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TC1130
Electrical Parameters
Data Sheet
85
V1.0, 2005-02
Advance Information
4.3.2
PLL Parameters
When PLL operation is configured (PLL_CLC.LOCK = 1), the on-chip phase locked loop
is enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor (N
Factor), and the output divider (F = NDIV+1 / (PDIV+1
× KDIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock, the frequency of fMC is constantly adjusted so
it is locked to fOSC. The slight variation causes a jitter of fMC which also affects the
duration of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency in order to correspond to the applied input
frequency (crystal or oscillator), the relative deviation for periods of more than one TCP
is lower than for one single TCP (see formula and Figure 4-3).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baud rates, etc.) the deviation caused by the PLL
jitter is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = KDIV+1) to generate the master clock signal fMC. Therefore, the
number of VCO cycles can be represented as K
× N, where N is the number of
consecutive fMC cycles (TCM).
For a period of N × TCM, the accumulated PLL jitter is defined by the corresponding
deviation D
N:
D
N [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D
3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K
× N < 95. For longer periods, the K×N=95 value can be
used. This steady value can be approximated by: D
Nmax [ns] = ±(1.5 + 600 / (K × fMC)).
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