參數(shù)資料
型號： SAF-TC1130-L150EBGREEN
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 150 MHz, MICROCONTROLLER, PBGA208
封裝： GREEN, PLASTIC, LBGA-208
文件頁數(shù)： 87/117頁
文件大?。?/td> 1726K
代理商： SAF-TC1130-L150EBGREEN
TC1130
Functional Description
Data Sheet
65
V1.0, 2005-02
Advance Information
3.23
On-Chip Debug Support
The On-Chip Debug Support of the TC1130 consists of the following building blocks:
OCDS L1 module of TriCore
OCDS L2 interface of TriCore
OCDS L1 module in the BCU of the FPI Bus
OCDS L1 facilities within the DMA
OCDS L2 interface of DMA
OCDS System Control Unit (OSCU)
Multi Core Break Switch (MCBS)
JTAG based Debug Interface (Cerberus JDI)
Suspend functionality of peripherals
Features:
TriCore L1 OCDS:
– Hardware event generation unit
– Break by DEBUG instruction or break signal
– Full Single-Step support in hardware, possible also with software break
– Access to memory, SFRs, etc. on the fly
DMA L1 OCDS:
– Output break request on errors
– Suspension of pre-selected channels
Level 2 trace port with 16 pins that outputs either TriCore, or DMA trace
OCDS System Control Unit (Cerberus OSCU)
– Minimum number of pins required (no OCDS enable pin)
– Hardware allows hot attach of a debugger to a running system
– System is secure (can be locked from internal)
Multi Core Break Switch (Cerberus MCBS):
– TriCore, DMA, break pins, and BCUs as break sources
– TriCore as break targets; other parts can in addition be suspended
– Synchronous stop and restart of the system
– Break to Suspend converter
Figure 3-15 shows a basic block diagram of the building blocks.
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