參數(shù)資料
型號(hào)： SAF-C515C-8EMCA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, MQFP-80
文件頁數(shù)： 85/97頁
文件大小： 1298K
代理商： SAF-C515C-8EMCA
C515C
Data Sheet
82
2003-02
Figure 34
SSC Timing
Notes:
1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is
valid for the other cases accordingly.
2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
3. In the case of master mode and CPHA = 0, the MSB becomes valid after the data
has been written into the shift register, i.e. at least one half SCLK clock cycle before
the first clock transition.
MCT02417
SCLK
STO
SRI
TC
t SCL
MSB
LSB
MSB
LSB
SCH
t
t SCLK
S
t
HI
t
~ ~
~~
~ ~
D
tt HD
DTC
t
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