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參數(shù)資料
| 型號(hào)： | SAF-C515C-8EMCA |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 43/97頁 |
| 文件大?。?/td> | 1298K |
| 代理商： | SAF-C515C-8EMCA |
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C515C
Data Sheet
44
2003-02
The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy
Check code to be transmitted after the data bytes and checks the CRC code of incoming
messages. This is done by dividing the data stream by the code generator polynomial.
The Error Management Logic (EML) is responsible for the fault confinement of the
CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are
incremented and decremented by commands from the Bit Stream Processor. According
to the values of the error counters, the CAN controller is set into the states error active,
error passive and busoff.
The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline
related bit timing according to the CAN protocol. The BTL synchronizes on a recessive
to dominant busline transition at Start of Frame (hard synchronization) and on any further
recessive to dominant busline transition, if the CAN controller itself does not transmit a
dominant bit (resynchronization). The BTL also provides programmable time segments
to compensate for the propagation delay time and for phase shifts and to define the
position of the Sample Point in the bit time. The programming of the BTL depends on the
baudrate and on external physical delay times.
The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message
objects of maximum 8 data bytes length. Each of these objects has a unique identifier
and its own set of control and status bits. After the initial configuration, the Intelligent
Memory can handle the reception and transmission of data without further CPU actions.
Switch-off Capability of the CAN Controller (C515C-8E only)
For power consumption reasons, the on-chip CAN controller in the C515C-8E can be
switched off by setting bit CSWO (bit 2) in SFR SYSCON. When the CAN controller is
switched off its clock signal is turned off and the operation of the CAN controller is
stopped. This switch-off state of the CAN controller is equal to its state in software power
down mode. After clearing bit CSWO again the CAN controller has to be reconfigured.
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| SAFC515C8EMCAT | 制造商:Infineon Technologies AG 功能描述:MCU 8-bit C500 8051 CISC 64KB EPROM 5V 80-Pin MQFP T/R |
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